View MCP3001_277821.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MCP3001
2.7V 10-Bit A/D Converter with SPITM Serial Interface
FEATURES
10-bit resolution 1 LSB max DNL 1 LSB max INL On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 200ksps sampling rate at 5V 75ksps sampling rate at 2.7V Low power CMOS technology - 5nA typical standby current, 2A max - 500A max active current at 5V * Industrial temp range: -40C to +85C * 8-pin PDIP, SOIC and TSSOP packages * * * * * * * * *
PACKAGE TYPES
PDIP
VREF IN+ IN- VSS 1 2 3 4 8 7 6 5 VDD CLK DOUT CS/SHDN
MCP3001
SOIC, TSSOP
VREF IN+ IN- VSS
APPLICATIONS
* * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems
1 2 3 4
8 7 6 5
FUNCTIONAL BLOCK DIAGRAM
VREF VDD VSS
MCP3001
VDD CLK DOUT CS/SHDN
DESCRIPTION
The Microchip Technology Inc. MCP3001 is a successive approximation 10-bit A/D converter (ADC) with on-board sample and hold circuitry. The device provides a single pseudo-differential input. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are both specified at 1 LSB max. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of sample rates of up to 200ksps at a clock rate of 2.8MHz. The MCP3001 operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with a typical standby current of only 5nA and a typical active current of 400A. The device is offered in 8 pin PDIP, TSSOP and 150mil SOIC packages.
DAC Comparator IN+ INSample and Hold Control Logic 10-Bit SAR
Shift Register
CS/SHDN
CLK
DOUT
SPI is a trademark of Motorola Inc.
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 1
MCP3001
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
NAME FUNCTION +2.7V to 5.5V Power Supply Ground Positive Analog Input Negative Analog Input Serial Clock Serial Data Out Chip select/Shutdown Input Reference Voltage Input
VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied......-65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ................................... > 4kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VDD VSS IN+ INCLK DOUT CS/SHDN VREF
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 200ksps and fCLK = 14*fSAMPLE unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25C unless otherwise noted. PARAMETER Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Reference Input Voltage Range Current Drain Analog Inputs Input Voltage Range (IN+) Input Voltage Range (IN-) Leakage Current Switch Resistance Sample Capacitor RSS CSAMPLE INVSS-100 0.001 1K 20 VREF+INVSS+100 1 V mV A pF See Figure 4-1 See Figure 4-1 0.25 90 0.001 VDD 150 3 V A A Note 2 CS = VDD = 5V -76 61 80 dB dB dB VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz INL DNL 10 0.5 0.25 1 1 1.5 1 bits LSB LSB LSB LSB No missing codes over temperature tCONV tSAMPLE fSAMPLE 1.5 200 75 10 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
DS21293A-page 2
Preliminary
2000 Microchip Technology Inc.
MCP3001
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 200ksps and fCLK = 14*fSAMPLE unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25C unless otherwise noted. PARAMETER Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (all inputs/outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements Operating Voltage Operating Current Standby Current VDD IDD IDDS 2.7 400 210 0.005 5.5 500 2 V A A A VDD = 5.0V, DOUT unloaded VDD = 2.7V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tDO tEN tDIS tCSH tR tF 350 100 100 160 160 100 125 200 125 200 100 2.8 1.05 MHz MHz ns ns ns ns ns ns ns ns ns ns ns See test circuits, Figure 1-2 (Note 1) See test circuits, Figure 1-2 (Note 1) VDD = 5V, See Figure 1-2 VDD = 2.7, See Figure 1-2 VDD = 5V, See Figure 1-2 VDD = 2.7, See Figure 1-2 See test circuits, Figure 1-2 (Note 1) VDD = 5V (Note 3) VDD = 2.7V (Note 3) VIH VIL VOH VOL ILI ILO CIN, COUT -- 4.1 -- -10 -10 -- Straight Binary 0.7 VDD -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1mA, VDD = 4.5V IOL = 1mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Note 1: This parameter is guaranteed by characterization and not 100% tested. 2: See graph that relates linearity performance to VREF level. 3: Because the sample cap will eventually lose charge, clock rates below 10kHz can affect linearity performance, especially at elevated temperatures.
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 3
MCP3001
tCSH
CS tSUCS tHI CLK tEN HI-Z tDO tR DOUT NULL BIT MSB OUT tF LSB HI-Z tDIS tLO
FIGURE 1-1:
Serial Timing. Load circuit for tR, tF, tDO
1.4V
Load circuit for tDIS and tEN
Test Point VDD
tDIS Waveform 2
VDD/2
3K DOUT
Test Point DOUT
3K 30pF
tEN Waveform tDIS Waveform 1
CL = 30pF
VSS
Voltage Waveforms for tR, tF
VOH VOL
Voltage Waveforms for tEN
DOUT
CS 1 CLK DOUT 2 3 4 B9
tR
tF
tEN Voltage Waveforms for tDO
CS
CLK
Voltage Waveforms for tDIS
VIH 90%
tDO
DOUT
DOUT Waveform 1*
tDIS
DOUT Waveform 2 10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control.
FIGURE 1-2:
Test Circuits.
DS21293A-page 4
Preliminary
2000 Microchip Technology Inc.
MCP3001
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
0.4 0.3 0.2
Positive INL
0.4 0.3
VDD = VREF = 2.7V Positive INL
INL (LSB)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 25 50 75 100 125 150 175 200 225 250
Negative INL
INL (LSB)
0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 25
Negative INL
50
75
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1: Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1
1.0 0.8 0.6
VDD = VREF= 2.7V fSAMPLE = 75ksps Positive INL
INL (LSB)
INL (LSB)
Positive INL
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
Negative INL
Negative INL
2
3
4
5
6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
VREF (V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. VREF.
FIGURE 2-5: (VDD = 2.7V)
Integral Nonlinearity (INL) vs. VREF .
0.5 0.4 0.3 0.2
VDD = VREF = 5V fSAMPLE = 200ksps
0.50 0.40 0.30 0.20
VDD = VREF = 2.7V fSAMPLE = 75ksps
INL (LSB)
INL (LSB)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 128 256 384 512 640 768 896 1024
0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0 128 256 384 512 640 768 896 1024
Digital Code
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 5
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
0.4 0.3
Positive INL
0.4 0.3 0.2
VDD = VREF = 2.7V fSAMPLE = 75ksps Positive INL
0.2
INL (LSB)
INL (LSB)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100
Negative INL
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100
Negative INL
Temperature (C)
Temperature (C)
FIGURE 2-7: Temperature.
Integral
Nonlinearity
(INL)
vs.
FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V).
(INL)
vs.
0.4 0.3 0.2 0.1 0.0 -0.1
Negative DNL Positive DNL
0.4 0.3 0.2
VDD = VREF = 2.7V
DNL (LSB)
DNL (LSB)
Positive DNL
0.1 0.0 -0.1 -0.2 -0.3 -0.4
Negative DNL
-0.2 -0.3 -0.4 0 25 50 75 100 125 150 175 200 225 250
0
25
50
75
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8: Differential Sample Rate.
Nonlinearity
(DNL)
vs.
FIGURE 2-11: Differential Nonlinearity Sample Rate (VDD = 2.7V).
(DNL)
vs.
1.0 0.8 0.6
1.0 0.8 0.6
Positive DNL
VDD = VREF = 2.7V fSAMPLE = 75ksps Positive DNL
DNL (LSB)
DNL (LSB)
0.4 0.2 0.0
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
-0.2 -0.4 -0.6 -0.8 -1.0 0 1 2
Negative DNL
Negative DNL
3
4
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
VREF (V)
FIGURE 2-9: VREF.
Differential
Nonlinearity
(DNL)
vs.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).
DS21293A-page 6
Preliminary
2000 Microchip Technology Inc.
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 128 256 384 512 640 768 896 1024
VDD = VREF = 5V fSAMPLE = 200 ksps
0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 128 256 384 512 640 768 896 1024
VDD = VREF = 2.7V fSAMPLE = 75 ksps
DNL (LSB)
DNL (LSB)
Digital Code
Digital Code
FIGURE 2-13: Differential Nonlinearity Code (Representative Part).
(DNL)
vs.
FIGURE 2-16: Differential Nonlinearity Code (Representative Part, VDD = 2.7V).
(DNL)
vs.
0.3 0.2
Positive DNL
0.3
VDD = VREF = 2.7V
0.2
fSAMPLE = 75ksps Positive DNL
DNL (LSB)
0.0 -0.1
Negative DNL
DNL (LSB)
0.1
0.1 0.0 -0.1
Negative DNL
-0.2 -0.3 -50 -25 0 25 50 75 100
-0.2 -0.3 -50 -25 0 25 50 75 100
Temperature (C)
Temperature (C)
FIGURE 2-14: Differential Temperature.
Nonlinearity
(DNL)
vs.
FIGURE 2-17: Differential Temperature (VDD = 2.7V).
Nonlinearity
(DNL)
vs.
1.0 0.8 VDD = 2.7V 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 2 3 4 5 VDD = 5V fSAMPLE = 200ksps
8 7
Offset Error (LSB)
Gain Error (LSB)
fSAMPLE = 75ksps
6 5 4 3 2 1 0 0.0
VDD = 5V f SAMPLE = 200ksps
VDD = 2.7V f SAMPLE = 75ksps
1.0
2.0
3.0
4.0
5.0
VREF (V)
VREF (V)
FIGURE 2-15: Gain Error vs. VREF.
FIGURE 2-18: Offset Error vs. VREF.
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 7
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
0.1
VDD = VREF = 2.7V
1.0 0.9
VDD = VREF = 5V fSAMPLE = 200ksps
Offset Error (LSB)
Gain Error (LSB)
0.0 -0.1 -0.2 -0.3 -0.4 -50
fSAMPLE = 75ksps
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
VDD = VREF = 2.7V fSAMPLE = 75ksps
VDD = VREF = 5V fSAMPLE = 200ksps
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (C)
Temperature (C)
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-22: Offset Error vs. Temperature.
70 60
70 60
SINAD (dB)
SNR (dB)
50 40 30 20 10 0 1 10 100
VDD = VREF = 2.7V fSAMPLE = 75ksps VDD = VREF = 5V fSAMPLE = 200ksps
50 40 30 20 10 0 1 10 100
VDD = VREF = 2.7V fSAMPLE = 75ksps VDD = VREF = 5V fSAMPLE = 200ksps
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-20: Frequency.
Signal to Noise Ratio (SNR) vs. Input
FIGURE 2-23: Signal to Noise (SINAD) vs. Input Frequency.
and
Distortion
THD (dB)
SINAD (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1
80 70
VDD = VREF = 2.7V fSAMPLE = 75ksps
60 50 40 30 20
VDD = VREF = 5V fSAMPLE = 200ksps
VDD = VREF = 5V fSAMPLE = 200ksps
VDD = VREF = 2.7V
10 0
fSAMPLE = 75ksps
10
100
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Frequency (kHz)
Input Signal Level (dB)
FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
FIGURE 2-24: Signal to Noise (SINAD) vs. Input Signal Level.
and
Distortion
DS21293A-page 8
Preliminary
2000 Microchip Technology Inc.
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
10.0 9.9 9.8
ENOB (rms)
9.7 9.6 9.5 9.4 9.3 9.2 9.1 9.0 0.0 1.0 2.0 3.0 4.0 5.0 VDD = VREF = 5V VDD = VREF = 2.7V fSAMPLE = 75ksps f SAMPLE = 200ksps
ENOB (rms)
10.0 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 1
VDD = VREF = 5V fSAMPLE = 200ksps
VDD = VREF = 2.7V fSAMPLE = 75ksps
10
100
V REF (V)
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs. VREF.
FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
VDD = VREF = 5V fSAMPLE = 200ksps
90 80 70 60 50 40 30 20 10 0 1 10
VDD = VREF = 2.7V fSAMPLE = 75ksps
Power Supply Rejection (dB)
100
0 -10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000
VDD = VREF = 5V fSAMPLE = 200ksps
SFDR (dB)
100
Ripple Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-26: Spurious Free (SFDR) vs. Input Frequency.
Dynamic
Range
FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 20000 40000
VDD = VREF = 5V FSAMPLE = 200ksps FINPUT = 10.0097kHz 4096 points
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000
VDD = VREF = 2.7V fSAMPLE = 75ksps fINPUT = 1.00708kHz 4096 points
Amplitude (dB)
60000
80000
100000
Amplitude (dB)
10000 15000 20000 25000 30000 35000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input (Representative Part).
FIGURE 2-30: Frequency Spectrum of 1kHz input (Representative Part, VDD = 2.7V).
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 9
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
500 450 400 350 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VREF = VDD All points at fCLK = 2.8Mhz except at VREF = VDD = 2.5V, fCLK =1.05Mhz
120 110 100 90 80 70 60 50 40 30 20 10 0
IREF (A)
IDD (A)
VREF = VDD All points at fCLK = 2.8Mhz except at VREF = VDD = 2.5V, fCLK = 1.05Mhz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 2-31: IDD vs. VDD.
FIGURE 2-34: IREF vs. VDD.
500 450 400 350 300 250 200 150 100 50 0 10 100 1000 10000
VDD = VREF = 2.7V VDD = VREF = 5V
120 110 100 90 80 70 60 50 40 30 20 10 0 10
VDD = VREF = 5V
IREF (A)
IDD (A)
VDD = VREF = 2.7V
100
1000
10000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency.
FIGURE 2-35: IREF vs. Clock Frequency.
IREF (A)
IDD (A)
600 550 500 450 400 350 300 250 200 150 100 50 0 -50
120 110
VDD = VREF = 5V fCLK = 2.8Mhz
VDD = VREF = 5V fCLK = 2.8Mhz
100 90 80 70 60 50 40 30 20 10 0
VDD = VREF = 2.7V fCLK = 1.05Mhz
VDD = VREF = 2.7V fCLK = 1.05Mhz
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (C)
Temperature (C)
FIGURE 2-33: IDD vs. Temperature.
FIGURE 2-36: IREF vs. Temperature.
DS21293A-page 10
Preliminary
2000 Microchip Technology Inc.
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200ksps, fCLK = 14*Sample Rate,TA = 25C
60
2.0
Analog Input Leakage (nA)
VREF = CS = VDD
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50
VDD = VREF = 5V
50 40
IDDS (pA)
30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-25
0
25
50
75
100
V DD (V)
Temperature (C)
FIGURE 2-37: IDDS vs. VDD.
FIGURE 2-39: Analog Input Leakage Current vs. Temperature.
100.00
VDD = VREF = CS = 5V
10.00
IDDS (nA)
1.00
0.10
0.01 -50 -25 0 25 50 75 100
Temperature (C)
FIGURE 2-38: IDDS vs. Temperature.
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 11
MCP3001
3.0
3.1
PIN DESCRIPTIONS
IN+
Positive analog input. This input can vary from IN- to VREF + IN-.
In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601, which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. If the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above Vss, then the 3FFh code will not be seen unless the IN+ input level goes above VREF level.
3.2
IN-
Negative analog input. This input can vary 100mV from VSS.
3.3
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.
3.4
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.
4.2
Reference Input
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.
The reference input (VREF) determines the analog input voltage range and the LSB size, as shown below. LSB Size = VREF 1024 As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is a function of the analog input signal and the reference input as shown below. Digital Output Code = 1024 * VIN VREF where: VIN = analog input voltage = V(IN+) - V(IN-) VREF = reference voltage When using an external voltage reference device, the system designer should always refer to the manufacturer's recomendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the ADC.
4.0
DEVICE OPERATION
The MCP3001 A/D converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock after CS has been pulled low. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 200ksps are possible on the MCP3001. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface.
4.1
Analog Inputs
The MCP3001 provides a single pseudo-differential input. The IN+ input can range from IN- to (VREF +IN-). The IN- input is limited to 100mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1.
DS21293A-page 12
Preliminary
2000 Microchip Technology Inc.
MCP3001
VDD RS CHx VT = 0.6V Sampling Switch SS RSS = 1k CSAMPLE = DAC capacitance = 20pF VSS
Legend VA RS CHx CPIN VT Ileakage
VA
CPIN 7pF
VT = 0.6V
Ileakage 1nA
= signal source = source impedance = input channel pad = input pin capacitance = threshold voltage = leakage current at the pin due to various junctions SS = sampling switch RSS = sampling switch resister CSAMPLE = sample/hold capacitance
FIGURE 4-1:
Analog Input Model.
4.0
Clock Frequency (Mhz)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 1000
VDD = VREF = 2.7V fSAMPLE = 75ksps
VDD = VREF = 5V fSAMPLE = 200ksps
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1LSB deviation in INL from nominal conditions.
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 13
MCP3001
5.0 SERIAL COMMUNICATIONS
Communication with the device is done using a standard SPI compatible serial interface. Initiating communication with the MCP3001 begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The device will begin to sample the analog input on the first rising edge after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit. The next 10 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If it is desired, the CS can be raised to end the conversion period at any time during the transmission. Faster conversion rates can be obtained by using this technique if not all the bits are captured before starting a new cycle. Some system designers use this method by capturing only the highest order 8 bits and `throwing away' the lower 2 bits.
tCYC tCSH
CS
tSUCS Power Down
CLK
tSAMPLE tCONV
NULL BIT
tDATA** B5 B4 B3 B2 B1 B0
*
DOUT
HI-Z
B9
B8
B7
B6
HI-Z
NULL BIT
B9
B8
B7
B6
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data, followed by zeros indefinitely. See Figure below. ** tDATA: during this time, the bias current and the comparator powers down and the reference input becomes a high impedance node.
FIGURE 5-1:
Communication with MCP3001 (MSB first Format).
tCYC tCSH
CS
tSUCS Power Down
CLK
tSAMPLE tCONV
NULL BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4
tDATA**
B5 B6 B7 B8 B9
DOUT
HI-Z
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefinitely. ** tDATA: during this time, the bias current and the comparator powers down and the reference input becomes a high impedance node leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2:
Communication with MCP3001 (LSB first Format).
DS21293A-page 14
Preliminary
2000 Microchip Technology Inc.
MCP3001
6.0
6.1
APPLICATIONS INFORMATION
Using the MCP3001 with Microcontroller SPI Ports
With most microcontroller SPI ports, it is required to clock out eight bits at a time. If this is the case, it will be necessary to provide more clocks than are required for the MCP3001. As an example, Figure 6-1 and Figure 6-2 show how the MCP3001 can be interfaced to a microcontroller with a standard SPI port. Since the MCP3001 always clocks data out on the falling edge of clock, the MCU SPI port must be configured to match this operation. SPI Mode 0,0 (clock idles low) and SPI Mode 1,1 (clock idles high) are both compatible with the MCP3001. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the CLK from the microcontroller idles in the `low' state. As shown in the diagram, the MSB is clocked out of the ADC on the falling edge of the third clock pulse. After the first eight clocks have been sent to the device, the microcontrol-
ler's receive buffer will contain two unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order five bits of the conversion. After the second eight clocks have been sent to the device, the MCU receive register will contain the lowest order five bits and the B1-B4 bits repeated as the ADC has begun to shift out LSB first data with the extra clocks. Typical procedure would then call for the lower order byte of data to be shifted right by three bits to remove the extra B1-B4 bits. The B9-B5 bits are then rotated 3 bits to the right with B7-B5 rotating from the high order byte to the lower order byte. Easier manipulation of the converted data can be obtained by using this method. Figure 6-2 shows SPI Mode 1,1 communication which requires that the clock idles in the high state. As with mode 0,0, the ADC outputs data on the falling edge of the clock and the MCU latches data from the ADC in on the rising edge of the clock.
CS
MCU latches data from ADC on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 Data is clocked out of ADC on falling edges
DOUT
HI-Z
NULL BIT B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3 B4
HI-Z
LSB first data begins to come out ? ? 0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3
Data stored into MCU receive register after transmission of first 8 bits
Data stored into MCU receive register after transmission of second 8 bits
FIGURE 6-1:
SPI Communication with the MCP3001 using 8 bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from ADC on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 Data is clocked out of ADC on falling edges
DOUT
HI-Z
NULL BIT B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
HI-Z
LSB first data begins to come out ? ? 0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3
Data stored into MCU receive register after transmission of first 8 bits
Data stored into MCU receive register after transmission of second 8 bits
FIGURE 6-2:
SPI Communication with the MCP3001 using 8 bit segments (Mode 1,1: SCLK idles high).
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 15
MCP3001
6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations
When the MCP3001 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample cap for 700s at VDD = 2.7V and 1.5ms at VDD = 5V. This means that at VDD = 2.7V, the time it takes to transmit the first 14 clocks must not exceed 700s. Failure to meet this criterion may induce linearity errors into the conversion outside the rated specifications. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using ADC, refer to AN-688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the ADC is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 where an op amp is used to drive, filter and gain the analog input of the MCP3001. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD
Device 4
Device 1
Device 3 Device 2
4.096V Reference
0.1F 100F 0.1F ADI REF198 VREF IN+
10F
1F
FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths.
MCP3001
R1 C1 R2 C2 R3 R4 MCP601 IN-
VIN
+ -
FIGURE 6-3: The MCP601 operational amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3001.
DS21293A-page 16
Preliminary
2000 Microchip Technology Inc.
MCP3001
MCP3001 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3001 - X /X
Package:
P = PDIP (8 lead) SN = SOIC (150 mil Body), 8 lead ST = TSSOP, 8 lead I = -40C to +85C MCP3001 = 10-Bit Serial A/D Converter MCP3001T = 10-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only)
Temperature Range: Device:
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 17
MCP3001
NOTES:
DS21293A-page 18
Preliminary
2000 Microchip Technology Inc.
MCP3001
NOTES:
2000 Microchip Technology Inc.
Preliminary
DS21293A-page 19
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Beijing
Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104
Taiwan
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
Denmark
Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Hong Kong
Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
France
Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Dallas
Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Detroit
Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835
01/21/00
Shanghai
Microchip Technology Unit B701, Far East International Plaza, No. 317, Xianxia Road Shanghai, 200051 P.R.C Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 2000 Microchip Technology Incorporated. Printed in the USA. 3/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
2000 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of MCP3001

	To Download MCP3001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .